CDBM CDBC Dual J-K Master Slave. Flip-Flop with Set and Reset. General Description. These dual J-K flip-flops are monolithic complementary. These dual J-K flip-flops are monolithic complementary. MOS (CMOS) integrated circuits constructed with N- and P- channel enhancement mode transistors. Pin−for−Pin Replacement for CDB. • NLV Prefix for dimensions section on page 2 of this data sheet. . Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3.

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For datasheft configurations this input is terminated to any of the logic levels, i. Pin 7 is the ground or negative supply input of the IC.

Set and Reset Inputs Pins 4, 6 and 10, 8: The IC can be also effectively used for datasbeet any load through input signals received from a sound sensor.

Here we can see how the above discussed operating principle of the IC is practically set up for a useful purpose.


This input is used for receiving clock signals which are normally in the form of square waves. The set up shown can be simply built with the help of the diagram.


The sets of outputs change states when operated in the bistable mode or while setting and resetting the IC, always producing opposite logic levels at any instant. The circuit shown can be used for toggling any load simply by touching the touch pad.

Datasheet(PDF) – TI store

Yet another important feature of the IC which enables the bistable operation through two different dataheet. Positive input Pin The configurations can be repeated by connecting the modules in series for getting the time period to any desired lengths, but in multiples of two.

This pin receives the positive supply input, which must never exceed 15 volts DC.

The signal may be applied externally through a transistor astable multivibrator or more conventional types using NAND gates or NOR gates. Gently adjust datasjeet fix the IC on the veroboard somewhere over the center of the board by soldering.

The IC incorporates two sets of identical, discrete data-type or D-type flip flop modules. The signals produces a bistable effect over one of the oc outputs, the other being connected to the Data input as explained above.


Pinouts of the IC The D-type blocks consist of four inputs, explained as follows: Pressing S2 now, just flips the status of the output to its original position.

The astable clocks can be witnessed through LED1. Data Input Pins 5 and 9: The diagram illustrates how a IC may be set up for testing its fundamental bistable operation and how it can be further applied for practical uses.

Complementary Ouputs Pins 1, 2, and 13, D-type flip flops refer to circuits which may have a couple of outputs that change or toggle states in response to triggers applied at the input terminals. After all the connections are made, have a quick glance and make sure that all have been wired as per the diagram, if possible brush-clean the solder side with thinner. Following conventional safety standards, primarily these datashee also need to be assigned to a logic level, preferably to the ground terminal for the present IC, via sufficiently high value resistors.

Clock Input Pins 3 and

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